The present invention relates to automatic testing equipment for evaluating the performance of integrated circuits prior to their shipment to customers and more specifically to the testing of integrated circuits for jitter.
Among other things as shown in FIG. 1A, testing equipment typically includes a large number of “test cards” (110 . . . 120) that each includes circuitry (112 . . . 114, 122 . . . 124) for communicating with one or more corresponding pins of an integrated circuit being tested. The integrated circuit is referred to in the art as the “device under test,” or “DUT”. Each pin (Pin A, Pin B etc.) of the DUT is associated with a separate channel (Channel A, Channel B etc.) on the test card. Each channel of a test card (110 . . . 120) may include pin electronics including a so-called “pin driver” for transmitting a test signal to its corresponding pin on the DUT. The pin electronics (112 . . . 114, 122 . . . 124) may also include a load, a precision measurement unit (PMU), a comparator and other electronics. The channel of the test card may also include an input path for receiving the output of the DUT. Normally associated with this input path is a comparator. To that end, the pin driver and the input path/comparator typically are connected to a corresponding pin via a relatively short transmission line.
Jitter is the deviation in or displacement of some aspect of the pulses in a digital signal. The deviation can be in terms of amplitude, phase timing, or the width of the signal pulse. Among the causes of jitter are electromagnetic interference (EMI) and crosstalk with other signals. As signal frequencies increase, jitter becomes a greater problem. For example in high speed serial communications such as PCI Express, FibreChannel and SONET jitter can result in data errors as timing accuracy is crucial.
In prior art automatic testing systems, precision time measurement equipment was an afterthought. For example, in certain prior art automatic testing equipment systems, the time measurement circuitry was separate on a separate board from the individual pin electronics and not associated with a specific channel. The time measurement circuitry was incorporated into the timing generator shared among multiple channels and was only capable of obtaining course time measurements due to a counter-based oversampling methodology. Other prior art systems have integrated more accurate time measurement equipment in the test head of the automated testing equipment however, the time measurement equipment was shared by all pins of a DUT and therefore the testing of jitter would require separate sequential tests for each pin. As a result, time measurement would take a substantial amount of time and therefore was cost ineffective.
Other testing companies have developed external testing equipment which can connect to one or more pins of a DUT, but these external timing measurement devices often fail due to errors caused by cable length and the communication time that is required for running a timing test. Further, these devices have a limited number of connections and as the pin count for DUTs grow, and the size of the DUTs decrease, complete timing tests cannot be performed on a single DUT without reconnecting the connections to separate pins of the DUT. Thus, the process for determining if jitter is present is inefficient.